1 idt74alvchg162282 3.3v cmos 18-bit to 36-bit registered bus exchanger commercial temperature range clk sel 1 b 1 c1 1d ce 1d c1 ce 1d c1 a 1 2 b 1 1 of 18 channels 39 40 25 24 27 oe 42 0 1 c1 1d dir 41 ce 1d c1 ce 1d c1 no no no no no t recommended t recommended t recommended t recommended t recommended for new designs for new designs for new designs for new designs for new designs july 2000 1999 integrated device technology, inc. dsc-4558/- c idt74alvchg162282 commercial temperature range 3.3v cmos 18-bit to 36-bit registered bus exchanger with 3-state outputs and bus-hold description: this 18-bit to 36-bit registered bus exchanger is manufactured using advanced dual metal cmos technology. the alvchg162282 is intended for use in applications in which data must be transferred from a narrow high- speed bus to a wide lower-frequency bus. applications: ? sdram modules ? pc motherboards ? workstations the alvchg162282 provides synchronous data exchange between the two ports. data is stored in the internal registers on the low-to-high transition of the clock (clk) input. for data transfer in the b-to-a direction, the select ( sel ) input selects 1b or 2b data for the a outputs. for data transfer in the a-to-b direction, a two-stage pipeline is provided in the 1b path, with a single storage register in the 2b path. data flow is controlled by the active-low output enable ( oe ) and the direction-control (dir) input. the dir control pin is registered to synchronize the bus direction changes with the clock. a port outputs have equivalent 50 ? series resistors. b port outputs have equivalent 20 ? series resistors. the switching characteristics in this spec, are based on 25pf (a port) and 80pf (b port) loads, but production test is accomplished with the standard 50pf load. the alvchg162282 has ?bus-hold? which retains the inputs? last state whenever the input bus goes to a high impedance. this prevents floating inputs and eliminates the need for pull-up/down resistors. functional block diagram features: ? 0.5 micron cmos technology ?typical t sk(0) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ? 0.40mm pitch tvsop package ? commercial range of 0c to +70c ?v cc = 3.3v 0.3v, normal range ? cmos power levels (0.4w typ. static) ? rail-to-rail output swing for increased noise margin ? low switching noise
commercial temperature range idt74alvchg162282 3.3v cmos 18-bit to 36-bit registered bus exchanger 2 gnd so80-1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 72 73 74 75 76 77 78 79 80 1 gnd 25 26 27 28 56 55 54 53 gnd a 1 a 4 v cc gnd v cc v cc 29 30 31 32 33 34 36 35 37 38 v cc gnd 52 51 50 49 48 47 46 gnd 45 44 43 gnd 39 42 40 41 2 b 9 v cc gnd gnd 1 b 10 2 b 10 1 b 9 2 b 8 gnd 1 b 8 1 b 7 2 b 7 2 b 6 1 b 6 2 b 5 1 b 5 gnd 2 b 4 1 b 4 2 b 3 1 b 3 v cc 2 b 2 1 b 2 2 b 1 1 b 1 a 2 a 3 a 5 a 6 a 7 a 9 a 8 clk sel 1 b 11 gnd 2 b 11 1 b 12 2 b 12 v cc 1 b 13 2 b 14 2 b 13 1 b 14 v cc v cc v cc dir oe 1 b 15 1 b 16 2 b 16 2 b 15 1 b 17 2 b 17 1 b 18 2 b 18 a 18 a 16 a 15 a 13 a 17 a 11 a 14 a 12 a 10 note: 1. as applicable to the device type. pin description note: 1. these pins have ?bus-hold.? all other pins are standard inputs, outputs, or i/os. tvsop top view pin configuration pin names description oe 3-state output enable input (active low) clk register input clock sel select input ax data inputs (1) or 3-state outputs xbx data inputs (1) or 3-state outputs dir direction control input capacitance (t a = +25 o c, f = 1.0mhz) absolute maximum ratings (1) symbol description max. unit v term (2) terminal voltage with respect to gnd ? 0.5 to + 4.6 v v term (3) terminal voltage with respect to gnd ? 0.5 to v cc + 0.5 v t stg storage temperature ? 65 to + 150 c i out dc output current ? 50 to + 50 ma i ik continuous clamp current, v i < 0 or v i > v cc 50 ma i ok continuous clamp current, v o < 0 ? 50 ma i cc i ss continuous current through each v cc or gnd 100 ma new16link notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminals. 3. all terminals except v cc . symbol parameter (1) conditions typ. max. unit c in control inputs v in = v cc or gnd 4 ? pf c out output capacitance v out = 0v 7 ? pf c i/o i/o port capacitance (a or b ports) v out = v cc or gnd 8.5 ? pf
3 idt74alvchg162282 3.3v cmos 18-bit to 36-bit registered bus exchanger commercial temperature range function tables (1) notes: 1. h = high voltage level l = low voltage level x = don?t care z = high-impedance = low-to-high transition 2. output level before indicated steady-state input conditions were established. 3. two clk edges are needed to propagate the data. 4. two clk edges are needed to propagate the data. the data is loaded in the first register when sel is low and propagates to the second register when sel is high. inputs outputs sel clk ax 1 bx 2 bx h x x 1 b 0 (2) 2 b 0 (2) l l l (3) l l h h (3) h a-to-b storage (oe = l, dir = h) b-to-a storage (oe = l, dir = l) output enable inputs outputs sel clk 1 bx 2 bx ax h x l l (4) h x h h (4) l l x l l h x h dc electrical characteristics over operating range (1) following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 3v to 3.6v 2 ? ? v v il input low voltage level v cc = 3v to 3.6v ? ? 0.8 v i ih input high current (2) v cc = 3.6v v i = v cc ?? 5a i il input low current (2) v cc = 3.6v v i = gnd ? ? 5 i ozh high impedance output current v cc = 3.6v v o = v cc ?? 10a i ozl (excludes bus-hold pins) v o = gnd ? ? 10 a v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl i cch i ccz quiescent power supply current v cc = 3.6v v in = gnd or v cc ?0.140a ? i cc quiescent power supply current variation one input at v cc ? 0.6v, other inputs at v cc or gnd v cc = 3-3.6v ? ? 750 a notes 1. typical values are at vcc = 3.3v, +25c ambient. 2. for control i/p?s only excludes bus-hold current. inputs outputs clk oe sel dir ax 1 bx, 2 bx hx x z z ll h zactive ll lactivez xlhx a 0 (2) 1b 0 -2b 0 (2)
commercial temperature range idt74alvchg162282 3.3v cmos 18-bit to 36-bit registered bus exchanger 4 bus-hold characteristics notes: 1. pins with bus-hold are identified in the pin description. 2. typical values are at v cc = 3.3v, +25c ambient. output drive characteristics operating characteristics, t a = 25 o c symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v (a port to b port) v cc = 3.0v i oh = ? 8ma 2 ? (b port to a port) i oh = ? 6ma 2 ? v ol output low voltage v cc = 3.0v to 3.6v i ol = 0.1ma ? 0.2 v (a port to b port) v cc = 3.0v i ol = 8ma ? 0.8 (b port to a port) i ol = 6ma ? 0.8 symbol parameter (1) test conditions min. typ. (2) max. unit i bhh bus-hold input sustain current v cc = 3.0v v i = 2.0v ? 75 ? ? a i bhl v i = 0.8v 75 ? ? i bhho bus-hold input overdrive current v cc = 3.6v v i = 0 to 3.6v ? ? 500 a i bhlo note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriate v cc range. t a = 0c to + 70c. v cc = 3.3v 0.3v symbol parameter test conditions typical unit c pd power dissipation capacitance outputs enabled c l = 0pf, f = 10mhz 80 pf c pd power dissipation capacitance outputs disabled 60 pf
5 idt74alvchg162282 3.3v cmos 18-bit to 36-bit registered bus exchanger commercial temperature range switching characteristics, c l = 25pf (a port), 80pf (b port) (1) v cc = 3.3v 0.3v symbol parameter min . max. unit t plh t phl propagation delay clk to ax 1.5 5 ns t plh t phl propagation delay clk to xbx 1.5 7.4 ns t pzh t pzl output enable time clk to ax 1.5 6.3 ns t pzh t pzl output enable time clk to xbx 1.5 9.4 ns t pzh t pzl output enable time oe to ax 1.5 6 ns t pzh t pzl output enable time oe to xbx 1.5 9.5 ns t phz t plz output disable time clk to ax 1.5 6.4 ns t phz t plz output disable time clk to xbx 1.5 7.8 ns t phz t plz output disable time oe to ax 1.5 5 ns t phz t plz output disable time oe to xbx 1.5 7.6 ns tsu setup time, high or low, ax data before clk 1.5 ? ns tsu setup time, high or low, xbx data before clk 2?ns tsu setup time, high or low, dir before clk 2?ns tsu setup time, high or low, sel before clk 2?ns t h hold time, high or low, ax data after clk 0.3 ? ns t h hold time, high or low, xbx data after clk 0.3 ? ns t h hold time, high or low, dir after clk 0.3 ? ns t h hold time, high or low, sel after clk 0.3 ? ns t w pulse duration, clk high or low 2.3 (2) ?ns f clock ? 160 mhz notes: 1. see test circuits and waveforms. t a = 0c to +70c. 2. this parameter is warranted but not production tested.
commercial temperature range idt74alvchg162282 3.3v cmos 18-bit to 36-bit registered bus exchanger 6 open v load gnd v cc pulse generator d.u.t. 500 ? 500 ? c l r t v in v out (1) alvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t alvc link data input 0v 0v 0v 0v t rem timing input synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t alvc link asynchronous control low-high-low pulse high-low-high pulse v t t w v t alvc link control input t plz 0v output normally low t pzh 0v switch vload output normally high enable disable switch gnd t phz 0v v ol + v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v oh - v hz alvc link test cir cuits and w a veforms test conditions propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. note: 1. diagram shown for input control enable-low and input control disable-high. pulse width note : 1. pulse generator for all pulses: rate 10mhz; tf 2.5ns; tr .5ns symbol v cc (1) = 3.3v 0.3v unit v load 6v v ih 2.7 v v t 1.5 v v lz 300 mv v hz 300 mv c l 25pf (a port), 80pf (b port) pf test switch disable low enable low v load disable high enable high gnd all other tests open
7 idt74alvchg162282 3.3v cmos 18-bit to 36-bit registered bus exchanger commercial temperature range *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. ordering information corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* idt xx alvc xxx xx package device type temp. range df g162 74 thin very small outline package (so80-1) 18-bit to 36-bit registered bus exchanger with 3-state outputs 0c to +70c xxxx family bus-hold 282 double-density with resistors bus-hold h
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